1. Field of the Invention
The present invention relates to a memory device using a semiconductor.
2. Description of the Related Art
Terms used in this specification will be briefly explained. First, when one of a source and a drain of a transistor is called a drain, the other is called a source in this specification. That is, they are not distinguished depending on the potential level. Therefore, a portion called a source in this specification can be alternatively referred to as a drain.
Further, even when it is written in this specification that “to be connected”, there is a case in which no physical connection is made in an actual circuit and a wiring is only extended. For example, in an insulated-gate field-effect transistor (hereinafter simply referred to as a transistor) circuit, there is a case in which one wiring serves as gates of a plurality of transistors. In this case, one wiring may have a plurality of branches to gates in a circuit diagram. In this specification, the expression “a wiring is connected to a gate” is also used to describe such a case.
Note that in this specification, in referring to a specific row, a specific column, or a specific position in a matrix, a reference sign is accompanied by a sign denoting coordinates as follows, for example: “a first selection transistor STr1_n_m”, “a bit line MBL_m”, and “a sub bit line SBL_n_m”. In the case where a row, a column, or a position is not specified, the case where elements are collectively referred to, or the case where the position is obvious, the following expressions may be used: “a first selection transistor STr1”, “a bit line MBL”, and “a sub bit line SBL” or simply “a first selection transistor”, “a bit line”, and “a sub bit line”.
A DRAM whose memory cell includes one transistor and one capacitor can be highly integrated, have no limit on the number of times of writing, and can perform writing and reading at relatively high speed; thus, such a DRAM is used in many kinds of electronic appliances. A DRAM stores data by accumulating electric charge in a capacitor of each memory cell, and reads the data by releasing the electric charge.
A conventional DRAM circuit is illustrated in FIG. 9. Similarly to the cases of other memory devices, memory cells are arranged in matrix. In FIG. 9, six memory cells in the n-th to the (n+5)-th rows and the m-th and the (m+1)-th columns and a driver circuit for reading are illustrated.
Hereinafter, the operation is briefly described. Data is written in the memory cells in the n-th row in the following manner. The potential of a word line WL_n is set to an appropriate potential (e.g., +1.8 V), so that transistors of the memory cells in the n-th row are turned on. Then, the potential of a bit line MBL such as a bit line MBL_m or a bit line MBL_m+1 is set to a potential (e.g., +1 V or 0 V) in accordance with data. This operation can be performed by setting of the potential of a data input/output terminal DATA of the driver circuit in FIG. 9. A capacitor of each memory cell is charged to the potential.
Data reading is more complex when compared to data writing. First, the potentials of all the bit lines MBL, including the bit lines MBL_m and MBL_m+1, are charged (precharged) to an appropriate potential (e.g., +0.5 V). This operation is performed by turning a first column transistor CTr1 on by controlling the potential of a first column driver line RL1 of the driver circuit in FIG. 9. The potential of a source of the first column transistor CTr1 is +0.5 V and a drain thereof is connected to the bit line MBL, whereby the bit line MBL is precharged to +0.5 V.
Both a high potential and a low potential of a power supply potential of the flip-flop circuit FF connected to the bit line MBL are set to +0.5 V. Note that a flip-flop circuit FF_m/m+1 functions as a sense amplifier which amplifies a potential difference between the bit line MBL_m and the bit line MBL_m+1. Flip-flop circuits are broadly used as sense amplifiers of DRAMs.
In that state, the potential of the word line in a row where reading is performed is controlled to be an appropriate potential, so that a transistor of the memory cell in the row is turned on. Accordingly, the potential of the bit line changes in accordance with the potential of the capacitor of the memory cell. For example, in order to perform reading of a memory cell in the (n+2)-th row, a word line WL_n+2 is set to the above potential.
In the case where a capacitor of a memory cell CL_(n+2)_m in the n+2-th row and the m-th column is charged to +1 V, the potential of the bit line MBL_m becomes higher than +0.5 V, e.g., +0.6 V. In the case where the capacitor is charged to 0 V, the potential of the bit line MBL_m becomes lower than +0.5 V, e.g., +0.4 V. On the other hand, in the bit line MBL_m+1, there is no memory cell connected to the word line WL_n+2; thus, the potential of the bit line MB_m+1 remains at +0.5 V.
In that state, the power supply potentials of the flip-flop circuit FF are set to predetermined values. For example, the high power supply potential is set to +1 V and the low power supply potential is set to 0 V here. The flip-flop circuit FF has a function of enlarging a difference between input potentials. For example, when the potential of a first terminal of the flip-flop circuit FF is higher than the potential of a second terminal of the flip-flop circuit FF, in the above condition, the potential of the first terminal becomes +1 V and that of the second terminal becomes 0 V.
Accordingly, when the potential of the bit line MBL_In is higher than +0.5 V, the potential of a terminal of the flip-flop circuit FF_m/m+1 which is connected to the bit line MBL_m becomes +1 V, and the potential of a terminal of the flip-flop circuit FF_m/m+1 which is connected to the bit line MBL_m+1 becomes 0 V. On the contrary, when the potential of the bit line MBL_m is lower than +0.5 V, the potential of the terminal of the flip-flop circuit FF_m/m+1 which is connected to the bit line MBL_m becomes 0 V, and the potential of the terminal of the flip-flop circuit FF_m/m+1 which is connected to the bit line MBL_m+1 becomes +1 V.
Since the bit line MBL_m is connected to the data input/output terminal DATA_m, data stored in a memory cell can be read by reading the potential of the data input/output terminal DATA_m. A problem in the above operation is reading accuracy. When parasitic capacitance (which is shown as CS_m or CS_m+1) of the bit line MBL is sufficiently smaller than the capacitance of the capacitor of the memory cell where reading is performed, the potential of the bit line MBL is substantially the same as the potential of the capacitor.
On the contrary, when the parasitic capacitance of the bit line MBL is larger than the capacitance of the capacitor of the memory cell, the potential of the bit line MBL becomes less likely to be affected by the potential of the capacitor. For example, if the parasitic capacitance of the bit line MBL is ten times as large as the capacitance of the capacitor, potential change is only approximately 0.05 V when electric charge accumulated in the capacitor is released to the bit line MBL by turning a transistor of the memory cell on.
The possibility of errors in the flip-flop circuit FF becomes higher as difference between input potentials becomes smaller. The bit line MBL, which intersects with many wirings, has larger parasitic capacitance as its length becomes longer. As the capacitance of the capacitor becomes relatively smaller than the parasitic capacitance of the bit line MBL, potential change becomes smaller; thus, errors easily occur at the time of reading.
Although the size of a memory cell tends to be reduced as miniaturization proceeds, the capacitance of a capacitor of the memory cell cannot be reduced because a predetermined ratio of the capacitance of the capacitor to the parasitic capacitance of a bit line needs to be kept in the above-described manner. In other words, while an area in which a capacitor is formed is reduced, the capacitor has been needed to have the same capacitance as a conventional capacitor.
At present, a capacitor is formed to have a trench structure in which a deep hole is formed in a silicon wafer or a stack structure in which a chimney-like projection is provided (see Non Patent Documents 1 and 2). Both the hole and the projection are needed to have an aspect ratio of 50 or more. That is, an extremely long and narrow structure body whose depth or height is 2 μm or more needs to be formed in a limited area, which is difficult to realize with high yield.
In order to overcome such a difficulty, a method is disclosed in which bit lines are provided with sub bit lines and a sense amplifier of a flip-flop circuit type is connected to each of the sub bit lines so that the capacitance of a capacitor is reduced (see Patent Document 1). However, the present inventor found that the semiconductor memory device disclosed in Patent Document 1 cannot stably operate and a malfunction easily occurs when capacitance (including parasitic capacitance), examples of which are the capacitance of a sub bit line, the capacitance of a capacitor connected to the sub bit line, and the capacitance of input of a flip-flop circuit, is 1 fF or less.
Such a malfunction is mainly caused by noise. For example, a case is considered where the potential of a circuit is changed by some noise. Potential change in a circuit is inversely proportional to the capacitance of the circuit. That is, when the same amount of potential change caused by noise is assumed, potential change caused by the noise can be ignored in the case where the capacitance of the circuit is large, but the potential greatly changes due to the noise in the case where the capacitance of the circuit is small.
In a usual DRAM, the capacitance of a bit line is several hundred fF or more. Thus, potential change of the bit line is limited even with very large noise. On the other hand, in a sub bit line the capacitance of which is 1 fF, a potential change as large as 0.1 V or more is caused by noise which would cause a potential change as small as 1 mV in a usual bit line. In a sub bit line the capacitance of which is 0.1 fF or less, potential change is as large as 1 V or more.
In many cases, such noise occurs in a short time and an adverse effect of such noise can be removed by accumulating data for a long time and averaging the data. However, when a flip-flop circuit or the like is incorporated, an adverse effect of noise comes to the surface. This is because the flip-flop circuit is a positive feedback circuit in which output of a first inverter is input of a second inverter and output of the second inverter is input of the first inverter.
In a positive feedback circuit, once predetermined potential difference is observed, even if the potential difference is temporary, the potential difference is amplified and fixed thereafter. That is, noise (mainly, thermal noise) which does not cause a problem in a usual DRAM causes a malfunction in a semiconductor memory device including a sub bit line whose capacitance is extremely small. Thus, the DRAM disclosed in Patent Document 1 cannot be used in the case where the capacitance of a capacitor is very small.
Further, when the capacitance of a capacitor is 10 fF or less, influence of the capacitance (which refers to, specifically, the capacitance of a gate of a transistor connected to an input terminal or the like, and is usually 1 fF or smaller, although dependent on the size of the transistor) of the input of the flip-flop circuit that is used for a sense amplifier cannot be ignored.
The potential of a bit line (or a sub bit line) changes by release of electric charge which is accumulated in a capacitor to the bit line (or the sub bit line). Potential change in the bit line (or the sub bit line) is caused also by change in the gate capacitance of a transistor in a flip-flop circuit, which is turned on/off during operation of the flip-flop circuit.
In the case of a usual DRAM, the capacitance of a capacitor is much larger than the capacitance of the input of the flip-flop circuit. Thus, it can be considered that change in the potential of the bit line is largely due to the capacitor. However, when the capacitance of the capacitor is ten or less times as large as the capacitance of the input of the flip-flop circuit, the flip-flop circuit is influenced by its gate capacitance and operation becomes unstable. Specifically, in a condition where the capacitance of the capacitor is two or less times as large as the capacitance of the input of the flip-flop circuit, it is almost impossible to control the flip-flop circuit in accordance with the capacitance of the capacitor.
Further, in a conventional semiconductor memory device including a sub bit line, for its structure in which off current of a transistor of a memory cell cannot be sufficiently reduced, a reduction in the capacitance of a capacitor simply causes a problem of an increase in the frequency of refreshing. For example, when the capacitance of the capacitor is 1 fF, which is one thirtieth of conventional capacitance, the frequency of refreshing needs to be 30 times as high as the conventional frequency of refreshing, in which case more power is consumed.